1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device selectively operating a plurality of divided memory blocks.
2. Description of the Background Art
FIG. 4 is a block diagram of a circuit showing a configuration of a conventional dynamic random access memory (hereinafter referred to as a "DRAM").
In FIG. 4, shown are two divided memory blocks 1 and 2 which are operated selectively, and a row selector 8 selecting respective row addresses of these memory blocks 1 and 2. Either memory block 1 or 2 is activated in response to an external address input.
Memory block 1 includes a plurality of memory cell arrays 1a-1c . . . , a plurality of bit line pairs BL1a, BL1a-BL1c, BL1c . . . , an input/output data line pair BUS1, BUS1, and a plurality of transfer gate transistors (each hereinafter referred to as a "transistor") 3a-3c . . . , 4a-4c . . . , 71 and 72.
Memory block 2 includes a plurality of memory cell arrays 2a-2c . . . , a plurality of bit line pairs BL2a, BL2a-BL2c, BL2c, an input/output data line pair BUS2, BUS2 and a plurality of transfer gate transistors (each hereinafter referred to as a "transistor") 5a-5c . . . , 6a-6c . . . , 73 and 74.
Since memory block 1 and memory block 2 are the same in configuration, description will be given of memory block 1 as an example.
Each of memory cell arrays 1a-1c . . . receives a bit line pair equalize signal BLEQ1, column select signals CS10-CS1N, and sense signals S10, S11, and operates in response to these signals.
Bit line pair equalize signal BLEQ1 brings paired bit lines provided in each of memory cell arrays 1a-1c . . . to the same potential when memory block 1 is in a non-selected state. Column select signals CS10-CS1N specify a column address corresponding to an external address input.
Sense signals S10, S11 amplify data of the column address specified by column select signals CS10-CS1N in each of memory cell arrays 1a-1c . . .
Memory cell arrays 1a-1c . . . are provided with bit line pairs BL1a, BL1a-BL1c, BL1c . . . , respectively. Input/output data line pair BUS1, BUS1 is for input/output of data between memory cell arrays 1a-1c . . . and the outside world.
Bit lines BL1a-BL1c . . . are connected to input/output data line BUS1 through transistors 3a-3c . . . , respectively. Bit lines BL1a-BL1c . . . are connected to input/output data line BUS1 through transistors 4a-4c . . . , respectively.
Input/output data line BUS1 is supplied with an internally generated Voltage V1 through transistors 71 and 72. Input/output data line BUS1 is supplied with internally generated voltage V1 through transistor 71. The internally generated voltage V1 determines respective initial charge potentials of input/output data lines BUS1, BUS1.
Transistors 71 and 72 receive a data line pair equalize signal DLEQ1 at their gates. The data line pair equalize signal DLEQ1 brings input/output data lines BUS1, BUS1 to the same potential when memory block 1 is in a non-selected state.
Row selector 8 generates row select signals RSa-RSc . . . for selecting a row address in response to an external address input. Row select signals RSa-RSc . . . correspond to respective row addresses of memory cell arrays 1a-1c . . .
Transistors 3a and 4a receive row select signal RSa at their gates. Transistor 3b and 4b receive row select signal RSb at their gates. Transistor 3c and 4c receive row select signal RSc at their gates.
As described above, memory block 2 is configured similar to memory block 1. Therefore, each of memory cell arrays 2a-2c receives a bit line pair equalize signal BLEQ2, column select signals CS20-CS2N, and sense signals S20, S21.
Transistors 73 and 74 receive an input/output data line pair equalize signal DLEQ2 at their gates.
Transistors 5a and 6a receive row select signal RSa at their gates. Transistors 5b and 6b receive row select signal RSb at their gates. Transistors 5c and 6c receive row select signal RSc at their gates.
Description will now be given of configuration of memory cell arrays 1a-1c . . . and 2a-2c . . . Since these memory cell arrays are the same in configuration, memory cell array 1a will be described as a representative example. In FIG. 5, the same portions as those of FIG. 4 are labeled with the same reference characters, and the description will not be repeated.
Referring to FIG. 5, the memory cell array includes a sense amplifier circuit SA, a memory portion M and an equalize circuit EQ.
Sense amplifier circuit SA includes three N channel transistors 26a-26c, and three P channel transistors 27a-27c. These transistors are provided between a power supply node N1 receiving power supply potential and a ground node N2 receiving ground potential, and between bit lines BL1a and BL1a.
Sense amplifier circuit SA receives sense signal S10 at the gate of transistor 26c, and sense signal S11 at the gate of transistor 27c. Sense amplifier circuit SA operates in response to sense signals S11 and S10, and amplifies the potential difference between bit lines BL1a and BL1a.
Memory portion M includes a plurality of memory cells MC0, MC1 . . . Each of memory cells MC0, MC1 . . . includes a capacitor and a transfer gate transistor (hereinafter referred to as a "transistor").
Each capacitor holds written electric charge in its capacity. Capacitors 28a, 28b . . . of memory cells MC0, MC1 . . . are connected to bit line BL1a or BL1a through corresponding transistors 29a, 29b . . . , respectively.
Capacitor 28a of memory cell MC0 is, for example, connected to bit line BL1a through transistor 29a. Capacitor 28b of memory cell MC1 is connected to bit line BL1a through transistor 29b.
Respective transistors 28a, 28b . . . of memory cells MC0, MC1 . . . receive corresponding column select signals CS10, CS11 . . . at their gates for operation.
Equalize circuit EQ includes transfer gate transistors 30a, 30b and 30c. Transistors 30a and 30b are connected in series between bit lines BL1a and BL1a. A node between transistors 30a and 30b is supplied with an internally generated voltage V2. The internally generated voltage V2 determines initial charge potentials of bit lines BL1a and BL1a.
Transistor 30c is connected between bit lines BL1a and BL1a. Transistors 30a-30c receive bit line equalize signal BLEQ1 at their gates for operation.
Operation of memory blocks 1 and 2 shown in FIGS. 4 and 5 will now be described. Memory block 1 is taken here as an example. In the following description, the cases where memory block 1 is in a non-selected state and in a selected state are described separately.
FIG. 6 is a timing chart showing operation of memory block 1 of the conventional DRAM shown in FIG. 4. Operation will be described here with reference to FIGS. 4 to 6.
[The case where memory block is not selected]
When memory block 1 is not selected, bit line pair equalize signal BLEQ1 of memory block 1 is brought to a logical high or H level. As a result, transistors 30a-30c of equalize circuit EQ in each of all memory cell arrays 1a-1c . . . configuring memory block 1 are turned on.
Consequently, bit line pair BL1a, BL1a is short-circuited by transistor 30c, and bit lines BL1a, BL1a attain the same potential.
Simultaneously, electric charge from internally generated voltage V2 is transmitted to bit lines BL1a, BL1a through transistors 30a and 30b, respectively. As a result, bit lines BL1a, BL1a are initially charged.
Similarly, data line pair equalize signal DLEQ2 is brought to the H level, and transistors 71 and 72 are turned on. As a result, input/output data lines BUS1, BUS1 are initially charged by internally generated voltage V1.
[The case where memory block is selected]
When memory block 1 is selected in response to an external address input, bit line pair equalize signal BLEQ1 of memory block 1 is brought to a logical low or L level. As a result, transistors 30a-30c of equalize circuit EQ in each of all memory cell arrays 1a-1c . . . configuring memory block 1 are turned off.
Consequently, in memory cell array 1a, for example, bit line pair BL1a, BL1a is not supplied with internally generated voltage V2. As a result, bit line pair BL1a, BL1a is brought to a complete floating state wherein the bit line pair is not supplied with electric charge at all. The same operation is carried out in each of the other memory cell arrays 1b, 1c . . .
Similarly, data line pair equalize signal DLEQ1 is also brought to the L level. In response to this, transistors 71 and 72 are both turned off. As a result, input/output data line pair BUS1, BUS1 is not supplied with internally generated voltage V1, and consequently brought to a complete floating state wherein the data line pair is not supplied with electric charge at all.
Then, a column select signal indicating a column address is applied to all memory cell arrays 1a-1c . . . configuring memory block 1. As a result, data of the column address is read out from all memory cell arrays 1a-1c . . .
One memory cell array represented by memory cell array 1a, for example, includes capacitors corresponding to a plurality of column select signals CS10-CS1N applied to memory block 1.
Therefore, if column select signal CS10 indicating column address=0 is selected, for example, transistor 29a is turned on, and the potential of bit line BL1a is changed due to electric charge stored in capacitor 28a.
As a result, a small potential difference is generated between bit line BL1a having the potential unchanged from the initial charge state and bit line BL1a having the potential changed.
Then, sense signals S10, S11 are applied. In response to this, transistors 26a-26c and 27a-27c configuring sense amplifier circuit SA are operated. As a result, the generated small potential difference is amplified by sense amplifier circuit SA, and consequently one of bit lines BL1a, BL1a is charged to the H level (VCC) and the other is discharged to the L level (GND). Bit line pairs of all memory cell arrays 1a-1c . . . are charged/discharged similar to the above.
Memory block 1 repeats such a selected state and non-selected state as described above alternately depending on whether it is selected or not in response to an external address input.
Memory block 2 operates similar to memory block 1.
What is important here is that 1/2 VCC is used as internally generated voltage V2 determining the initial charge potential of a bit line pair when memory blocks 1 and 2 are in a non-selected state in operation of the conventional memory cell array.
This is because 1/2 VCC is less likely to be affected by noise of the power supply source (VCC, GND), and because current consumption is low when 1/2 VCC is used for initial charge.
As described above, memory blocks 1 and 2 are independent memory blocks which can be selectively operated.
Description will now be given of actual operation of reading data externally from memory block 1 in the DRAM shown in FIG. 4.
When a predetermined column address is selected in response to an external address input, memory block 1 having the column address is selected. As a result, data of a capacitor corresponding to column address=0 is read out in all memory cell arrays 1a-1c . . . based on column select signal CS10. The read data is amplified by sense amplifier circuit SA.
In response to data line equalize signal DLEQ1 attaining the L level, input/output data line pair BUS1, BUS1 is not supplied with internally generated voltage V1, and brought to a floating state.
After that, a row address is selected in response to an external address input. Therefore, a row select signal corresponding to the row address is selected by row selector 8, and brought to the H level. Description is given here on the assumption that a row select signal RSb is selected.
In row selector 8, bit line pair BL1b, BL1b of memory cell array 1b corresponding to the row address of row select signal RSb out of all memory cell arrays 1a-1c . . . amplifying data corresponding to column address=0 and input/output data line pair BUS1, BUS1 are connected in response to row select signal RSb.
As a result, one of the input/output data lines is charged to the H level (VCC) and the other is discharged to the L level (GND) by sense amplifier circuit SA in memory cell array 1b, whereby data is read out.
When memory block 1 is in a selected state in such reading of data, memory block 2 which is not selected is always in a non-selected state. Therefore, in this case, respective bit line pairs BL2a, BL2a-BL2c, BL2c of memory cell arrays 2a-2c and input/output data line pair BUS2, BUS2 in memory block 2 are always initially charged.
What is characteristic in such a conventional DRAM is that not only a bit line pair of a memory block in a selected state but also a bit line pair of a memory block in a non-selected state is connected to an input/output data line pair in response to row select signals RSa-RSc generated by row selector 8.
In the conventional case, internally generated voltage V2 for initial charge of a bit line pair is the same as internally generated voltage V1 for initial charge of an input/output data line pair.
Description will now be given of the case where there is a potential difference between internally generated voltages V1 and V2.
More specifically, description will be given on the assumption that initial charge potential v1 of an input/output data line pair is set higher than initial charge potential V2 of a bit line pair (for example, the case where each bit line pair is set to 1/2 VCC, and each input/output data line pair is set higher than 1/2 VCC).
In this case, in selected memory block 1, before select signal CS10 is selected, the bit line pair is not supplied with internally generated voltage V2 and data has been already amplified by sense amplifier circuit SA in each of memory cell arrays 1a-1c . . . , as described above.
In response to data line equalize signal DLEQ1 attaining the L level, input/output data line pair BUS1, BUS1 is not supplied with internally generated voltage V1, and brought to a floating state.
Therefore, when bit line pair BL1b, BL1b and input/output data line pair BUS1, BUS1 are connected because of on operation of transistors 3b, 4b in response to row select signal RSb, for example, sense amplifier circuit SA causes only a current charging/discharging electric charge of input/output data line pair BUS1, BUS1 in a floating state to flow.
In this case, since memory block 2 is in a non-selected state, however, both bit line pair equalize signal BLEQ2 and data line pair equalize signal DLEQ2 are at the H level.
Since transistors 5b, 6b are turned on in this case, internally generated voltage V1 is still supplied to input/output data line pair BUS2, BUS2. Internally generated voltage V2 is still-supplied to bit line pairs BL2a, BL2a-BL2c,BL2c . . .
Therefore, while row select signal RSb is selected, for example, a potential difference between internally generated voltages V1 and V2 causes a current to flow. As a result, current consumption is increased.
In order to prevent such current flow, both data line equalize signal DLEQ2 and bit line pair equalize signal BLEQ2 are brought to the L level also in memory block 2 while memory block 1 is selected. As a result, bit line pairs BL2a, BL2a-BL2c, BL2c . . . and input/output data line pair BUS2, BUS2 are not supplied with internally generated voltages V1 and V2, respectively.
As described above, input/output data line pair BUS2, BUS2 and bit line pairs BL2a, BL2a-BL2c, BL2c . . . in memory block 2 are kept in a floating state at respective initial charge potentials.
As a result, when a row select signal is selected, such a current as described above will not flow in a memory block in a non-selected state.
Since input/output data line pair BUS2, BUS2 and bit line pairs BL2a, BL2a-BL2c, BL2c . . . in a floating state at different initial charge potentials are connected, electric charge is averaged between these line pairs, thereby bringing these line pairs to the same potential.
In such a condition, during a period from end of operation of a selected memory block to start of the next operation, the bit line pair must be again charged to the potential of 1/2 VCC, and the input/output data line pair must be initially charged to the potential higher than 1/2 VCC. Therefore, current consumption is increased.
Further, in such a case, every time any of row select signals RSa-RSc . . . is selected, the potential of a bit line pair of a memory block in a non-selected state corresponding to the selected row is changed under the influence of the input/output data line pair.
Further, as shown in FIG. 5, the bit line pair is connected to a capacitor storing data only through a transfer gate transistor. Therefore, such inadvertent potential change of a bit line pair generates noise or the like, causing destruction of data held by the capacitor.
In such a conventional DRAM selectively operating divided memory blocks as described above, not only a bit line pair in a memory block in a selected state (block including a capacitor in which it is desired to externally input/output data) but also a bit line pair in a memory block in a non-selected state (block not including a capacitor in which it is desired to externally input/output data) is connected to an input/output data line pair in each memory block in response to respective row select signals RSa-RSc . . . generated from row selector 8.
Therefore, it was not easy to operate selectively divided memory blocks with a potential difference between the initial charge potential of each bit line pair (conventionally 1/2 VCC) and the initial charge potential of each input/output data line pair connected thereto.